The formation of ultra-shallow p.sup.+ and n.sup.+ doped regions within the silicon substrate is a crucial step in the fabrication of metal-oxide semiconductor (MOS) transistors and other semiconductor devices used within integrated circuits. The ever-decreasing size of MOS transistors requires a downscaling of all lateral and vertical dimensions of the transistor. In conventional scaling scenarios, the depth of the junctions, which form the source and drain regions of MOS transistors, scales linearly with gate length. Therefore, shallower junctions of p.sup.+ and n.sup.+ regions which have suitably low sheet resistance are required in the present semiconductor manufacturing industry.
In conventional semiconductor manufacturing processes, shallow junctions may be formed by ion implantation followed by an anneal such as a rapid thermal anneal (RTA). The reliability of this technique is known in the art down to a junction depth of 300 to 400 angstroms. The task of producing a doped region having both a junction depth of less than 300 or 400 angstroms and a suitably low sheet resistance is more challenging. This task is rendered particularly difficult for p-type shallow doped regions by the implant and diffusion properties of boron, in particular. Crucial issues include control of dopant channeling, reduction of thermal diffusion, and suppression of transient-enhanced diffusion, especially in the case of boron and phosphorus. Moreover, good device performance is only attained with a low sheet resistance of the shallow regions (i.e., with a high impurity concentration). The scaling tendency has been to reduce the ion implant energy while the total dopant level is kept more or less constant, and to reduce the thermal budget without significantly deteriorating the dopant activation level by introducing rapid thermal anneals and spike anneals.
This conventional scaling is expected to become difficult below the 300 to 400 angstrom junction depths, particularly for p.sup.+ junctions. The technical difficulty in making a high-current, low-energy ion implantation beam may be alleviated by the use of plasma doping (alternatively called plasma immersion ion implantation). Alternative processes that avoid implantation altogether have also been considered. Examples of such processes include rapid thermal vapor phase doping, gas immersion laser doping, and solid state hot diffusion such as from a BSG (boro-silicate glass), PSG (phosphorus silicon glass), or ASG (arsenic silicon glass) film. All of these processes face one or more problems with manufacturability.
Another process for producing doped regions having shallow junctions includes outdiffusion from an implanted oxide. According to this process, a thin oxide on top of the silicon is implanted with a high dose of boron or phosphorus so as to confine the dopant within the oxide. During a subsequent RTA step, the dopant is driven into the silicon. This process relies on a high concentration of boron or phosphorus in the oxide to provide for sufficient dopant diffusion through the Si--SiO.sub.2 interface and into the silicon. Therefore, given the limitations and capabilities of available ion implantation equipment, this process is only practical for use in conjunction with an oxide that is thinner than 100 angstroms. The required high dosage may produce defects within the silicon substrate.
Recent attempts to optimize this process have placed the dopant peak concentration near the top surface of the oxide for fear of creating defects within the silicon, due to high dosage amounts. Such defects may remain within the silicon even after a subsequent annealing process is completed. Recent attempts to use this technique are also limited because nearly all of the implanted species must be implanted into the oxide, and not into the underlying silicon, to avoid the problem of defects. As a consequence, all of the implanted species which diffuse into the silicon during anneal originate from within the oxide film. Because the peak concentration of the implanted species is near the top surface of the oxide film, the annealing process is necessarily a time-consuming process in order to allow for the diffusion of the implanted species from near the upper surface of the oxide film into the silicon. Alternatively, a high dose would be required to achieve a suitably low sheet resistance. Such a high dose is undesirable, however, because defects may result in the silicon substrate.
What is needed is a structure, and a process for producing the structure, that provides a maximum doping of the silicon to produce a suitably low sheet resistance. The process should use a reduced annealing time, a reduced dose, or both a reduced annealing time and a reduced dose with a corresponding reduced implant time. The need is to produce a doped region that has an ultra-shallow junction depth and is substantially defect-free.